Tantalum pentoxide (Ta.sub.2 O.sub.5) is a desired capacitor dielectric material due to its high dielectric constant of about 25. In contrast, other commonly utilized dielectric materials have much lower dielectric constants. For instance, silicon nitride has a dielectric constant of about 8 and silicon dioxide has a dielectric constant of about 4. Due to the high dielectric constant of Ta.sub.2 O.sub.5, a thinner layer of Ta.sub.2 O.sub.5 can be utilized in capacitor constructions to achieve the same capacitance as thicker layers of other materials.
Semiconductive capacitors comprise a first conductive plate and a second conductive plate, with a dielectric layer formed between the plates. Commonly, the conductive plates comprise doped polysilicon, with one or both of the plates comprising a rugged form of polysilicon, such as, for example, hemispherical grain polysilicon.
It is highly desired to utilize Ta.sub.2 O.sub.5 as the dielectric layer due to the dielectric properties discussed above. Unfortunately, the chemical vapor deposition (CVD) processes by which Ta.sub.2 O.sub.5 is formed adversely complicate its incorporation into semiconductive capacitors. For instance, Ta.sub.2 O.sub.5 is not typically deposited onto a first polysilicon plate, nor is a second polysilicon plate-typically directly deposited onto Ta.sub.2 O.sub.5. The CVD processes by which Ta.sub.2 O.sub.5 is formed adversely affect underlying and overlying polysilicon layers unless such polysilicon layers are first protected with barrier layers. Specifically, Ta.sub.2 O.sub.5 is typically formed by a CVD process in which Ta(OC.sub.2 H.sub.5).sub.5 and oxygen are combined. Unless a polysilicon plate is protected by a barrier layer before such CVD deposition over the polysilicon, the oxygen of the CVD process will react with the polysilicon to disadvantageously form a layer of silicon dioxide over the polysilicon. Present methods for protecting the polysilicon include provision of a silicon nitride layer over the polysilicon prior to formation of Ta.sub.2 O.sub.5. The silicon nitride layer is typically 10 to 20 angstroms thick. Also, unless a Ta.sub.2 O.sub.5 layer is first covered with a barrier layer before formation of polysilicon over the Ta.sub.2 O.sub.5 layer, the polysilicon will react with oxygen in the Ta.sub.2 O.sub.5 layer to disadvantageously form silicon dioxide.
An example prior art process for forming a capacitor 10 having a Ta.sub.2 O.sub.5 dielectric layer is illustrated in FIG. 1. A polysilicon first capacitor plate 12 is formed over a substrate 14. A silicon nitride layer 16 is formed over polysilicon layer 12. A Ta.sub.2 O.sub.5 dielectric layer 18 is formed over silicon nitride layer 16 by the above-described CVD process. After the CVD of Ta.sub.2 O.sub.5 layer 18, the layer is typically subjected to an anneal in the presence of an oxygen ambient. The anneal drives any carbon present in layer 18 out of the layer and advantageously injects additional oxygen into layer 18 such that the layer uniformly approaches a stoichiometry of five oxygen atoms for every two tantalum atoms. The oxygen anneal is commonly conducted at a temperature of from about 400.degree. C. to about 1000.degree. C. utilizing an ambient comprising an oxygen containing gas. The oxygen containing gas commonly comprises one or more of O.sub.3, N.sub.2 O and O.sub.2. The oxygen containing gas is typically flowed through a reactor at a rate of from about 0.5 slm to about 10 slm.
Ta.sub.2 O.sub.5 layer 18 is typically from about 40 angstroms to about 150 angstroms thick and can be either amorphous or crystalline. It is noted that Ta.sub.2 O.sub.5 is generally amorphous if formed below 600.degree. C. and will be crystalline if formed, or later processed, at or above 600.degree. C. Typically, a Ta.sub.2 O.sub.5 layer is deposited as an amorphous layer and the above-described oxygen anneal is conducted at a temperature of 600.degree. C. or greater to convert the amorphous Ta.sub.2 O.sub.5 layer to a crystalline layer.
A second nitride layer 20 is deposited over Ta.sub.2 O.sub.5 layer 18. Second nitride layer 20 typically comprises TiN or WN. A second capacitor plate 22 is formed over nitride layer 20. Second capacitor plate 22, like first capacitor - plate 12, typically comprises doped polysilicon or doped rugged polysilicon. It is noted that the top electrode of the Ta.sub.2 O.sub.5 capacitor can comprise only TiN or WN layer 20, or can comprise the layer 20 and layer 22 stack.
The formation of layer 20 is typically done by a chemical vapor deposition process, as opposed to a sputtering type process, to achieve acceptable conformity in high aspect ratio capacitor devices. Such CVD processes use either metal organic precursors or organometallic precursors. Either precursor contains carbon and results in the deposition of a barrier layer 20 which typically includes large amounts of carbon, commonly from about 10 to about 15 volume percent, and sometimes as much as 30 volume percent. Although such carbon typically does not adversely impact the function or conductivity of the nitride layer 20, subsequent wafer processing can cause carbon from layer 20 to diffuse into Ta.sub.2 O.sub.5 layer 18. Carbon diffusing into Ta.sub.2 O.sub.5 layer 18 can disadvantageously cause layer 18 to leak current, and in extreme cases can convert an intended capacitor device 10 into a device that behaves more like a resistor than a capacitor.
An additional disadvantage that can occur during placement of a nitride barrier layer 20 over Ta.sub.2 O.sub.5 layer 18 is that there is typically some formation of the undesired compound TiO.sub.2 at an interface between Ta.sub.2 O.sub.5 layer 18 and barrier layer 20.
It would be desirable to develop alternative methods of utilizing Ta.sub.2 O.sub.5 in integrated circuit construction.